This white LED lamp lets you use your PC or laptop at night without disturbing others’ sleep. It produces a soft white light just enough to see the keyboard in darkness as well as when the ambient light is poor during daytime. The circuit is powered by regulated 5V DC available from the USB socket of the PC. LDR1 acts as a light-dependent switch to turn on the lamp (LED2 through LED7) when the ambient light in the room drops below the preset level. Transistors T1 and T2 (BC547) are used to switch on the lamp. The base of transistor T1 is connected to the voltage divider comprising LDR1 and preset VR1. When light in the room is sufficient, the resistance of LDR1 is low. This results in a high voltage at the base of T1, driving it into saturation. When transistor T1 conducts, transistor T2 is cut off. This disconnects the power supply to all the white LEDs (LED2 through LED7). LED1 (green LED) glows as it is forward-biased, indicating the standby mode.
When it is dark, or the ambient light in the room is lesser than the pre-determined level set by VR1, transistor T1 is cut off and T2 conducts. All the white LEDs glow with sufficient brightness as these are connected to the power supply through series dropper resistors R2 through R7. These resistors are used to limit the current through white LEDs to a safe level.
In the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a binary divider, for Frequency Division or as a "divide-by-2" counter. Here the inverted output terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device "feedback" as shown below.
Divide-by-2 Counter
It can be seen from the frequency waveforms above, that by "feeding back" the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( f÷2 ) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave). This then produces a type of counter called a "ripple counter" and in ripple counters, the clock pulse triggers the first flip-flop whose output triggers the second flip-flop, which inturn triggers the third flip-flop and so on through the chain.
Toggle Flip-Flop
Another type of device that can be used for frequency division is the T-type or Toggle flip-flop. With a slight modification to a standard JK flip-flop, we can construct a new type of flip-flop called a Toggle flip-flop were the two inputs J and k of a JK flip-flop are connected together resulting in a device with only two inputs, the "Toggle" input itself and the controlling "Clock" input. The name "Toggle flip-flop" indicates the fact that the flip-flop has the ability to toggle between its two states, the "toggle state" and the "memory state". Since there are only two states, a T-type flip-flop is ideal for use in frequency division and counter design.
Binary ripple counters can be built using "Toggle" or "T-type flip-flops" by connecting the output of one to the clock input of the next. Toggle flip-flops are ideal for building ripple counters as it toggles from one state to the next, (HIGH to LOW or LOW to HIGH) at every clock cycle so simple frequency divider and ripple counter circuits can easily be constructed using standard T-type flip-flop circuits.
If we connect together in series, two T-type flip-flops the initial input frequency will be "divided-by-two" by the first flip-flop ( f÷2 ) and then "divided-by-two" again by the second flip-flop ( f÷2 )÷2, giving an output frequency which has effectively been divided four times, then its output frequency becomes one quarter value (25%) of the original clock frequency, ( f÷4 ). Each time we add another toggle or "T-type" flip-flop the output clock frequency is halved or divided-by-2 again and so on, giving an output frequency of 2nwhere "n" is the number of flip-flops used in the sequence.
Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon the standard JK-type flip flop and which is triggered on the rising edge of the clock signal. The result is that each bit moves right by one flip-flop. All the flip-flops can be asynchronously reset and can be triggered to switch on either the leading or trailing edge of the input clock signal making it ideal for Frequency Division.
Frequency Division using Toggle Flip-flops
This type of counter circuit used for frequency division is commonly known as an Asynchronous 3-bit Binary Counter as the output on QA to QC, which is 3 bits wide, is a binary count from 0 to 7 for each clock pulse. In an asynchronous counter, the clock is applied only to the first stage with the output of one flip-flop stage providing the clocking signal for the next flip-flop stage and subsequent stages derive the clock from the previous stage with the clock pulse being halved by each stage.
This arrangement is commonly known as Asynchronous as each clocking event occurs independently as all the bits in the counter do not all change at the same time. As the counter counts sequentially in an upwards direction from 0 to 7. This type of counter is also known as an "up" or "forward" counter (CTU) or a "3-bit Asynchronous Up Counter". The three-bit asynchronous counter shown is typical and uses flip-flops in the toggle mode. Asynchronous "Down" counters (CTD) are also available.
Truth Table for a 3-bit Asynchronous Up Counter
Clock Cycle
Output bit Pattern
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
Then we can see that the output from the D-type flip-flop is at half the frequency of the input, in other words it counts in 2's. By cascading together more D-type or Toggle Flip-Flops, we can produce a divide-by-2, divide-by-4, divide-by-8, etc. circuit which will divide the input clock frequency by 2, 4 or 8 times, in fact any value to the power-of-2 we want making a binary counter circuit.
Counters
Then a counter is nothing more than a specialised register or pattern generator that produces a specified output pattern or sequence of binary values (or states) upon the application of an input pulse signal called the "Clock". The clock is actually used for data transfer in these applications. Typically, counters are logic circuits that can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal.
Counters are formed by connecting flip-flops together and any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter where "n" is the number of counter stages used and which is called the Modulus. The modulus or simply "MOD" of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one complete cycle.
Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2n-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.
An example of this is given as.
3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)
4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)
The Modulo number can be increased by adding more flip-flops to the counter and cascading is a method of achieving higher modulus counters. Then the modulo or MOD number can simply be written as: MOD number = 2n
4-bit Modulo-16 Counter
Multi-bit asynchronous counters connected in this manner are also called "Ripple Counters" or ripple dividers because the change of state at each stage appears to "ripple" itself through the counter from the LSB output to its MSB output connection. Ripple counters are available in standard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built in clock oscillator and produce excellent frequency division of the fundamental frequency.
Frequency Division Summary
For frequency division, toggle mode flip-flops are used in a chain as a divide by two counter. One flip-flop will divide the clock, ƒin by 2, two flip-flops will divide ƒin by 4 (and so on). One benefit of using toggle flip-flops for frequency division is that the output at any point has an exact 50% duty cycle.
The final output clock signal will have a frequency value equal to the input clock frequency divided by the MOD number of the counter. Such circuits are known as "divide-by-n" counters. Counters can be formed by connecting individual flip-flops together and are classified according to the way they are clocked.
In Asynchronous counters, (ripple counter) the first flip-flop is clocked by the external clock pulse and then each successive flip-flop is clocked by the output of the preceding flip-flop. In Synchronous counters, the clock input is connected to all of the flip-flop so that they are clocked simultaneously.
Asynchronous Counter
In the previous tutorial we saw that an Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16 for a 4-bit counter, (0-15) making it ideal for use in Frequency Division. But it is also possible to use the basic asynchronous counter to construct special counters with counting states less than their maximum output number by forcing the counter to reset itself to zero at a pre-determined value producing a type of asynchronous counter that has truncated sequences. Then an n-bit counter that counts up to its maximum modulus (2n) is called a full sequence counter and a n-bit counter whose modulus is less than the maximum possible is called a truncated counter.
But why would we want to create an asynchronous truncated counter that is not a MOD-4, MOD-8, or some other modulus that is equal to the power of two. The answer is that we can by using combinational logic to take advantage of the asynchronous inputs on the flip-flop. If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits.
Such counters are generally referred to as Decade Counters. A decade counter requires resetting to zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this condition back to the reset input. A counter with a count sequence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common.
Asynchronous Decade Counter
This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops.
This signal causes all of the Q outputs to be reset back to binary "0000" on the count of 10. Once QB andQD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". We now have a decade or Modulo-10 counter.
Decade Counter Truth Table
Clock Count
Output bit Pattern
Decimal Value
QD
QC
QB
QA
1
0
0
0
0
0
2
0
0
0
1
1
3
0
0
1
0
2
4
0
0
1
1
3
5
0
1
0
0
4
6
0
1
0
1
5
7
0
1
1
0
6
8
0
1
1
1
7
9
1
0
0
0
8
10
1
0
0
1
9
11
Counter Resets its Outputs back to Zero
Decade Counter Timing Diagram
Using the same idea of truncating counter output sequences, the above circuit could easily be adapted to other counting cycles be simply changing the connections to the AND gate. For example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the AND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100" and that output "QA" is the least significant bit (LSB).
Since the maximum modulus that can be implemented with n flip-flops is 2n, this means that when you are designing truncated asynchronous counters you should determine the lowest power of two that is greater than or equal to your desired modulus. For example, lets say you wish to count from 0 to 39, or mod-40. Then the highest number of flip-flops required would be six, n = 6 giving a maximum MOD of 64 as five flip-flops would only equal MOD-32.
Now suppose we wanted to build a "divide-by-128" counter for frequency division we would need to cascade seven flip-flops since 128 = 27. Using dual flip-flops such as the 74LS74 we would still need four IC's to complete the circuit.
One easy alternative method would be to use two TTL 7493's as 4-bit ripple counter/dividers. Since 128 = 16 x 8, one 7493 could be configured as a "divide-by-16" counter and the other as a "divide-by-8" counter. The two IC's would be cascaded together to form a "divide-by-128" frequency divider as shown.
Of course standard IC asynchronous counters are available such as the TTL 74LS90 programmable ripple counter/divider which can be configured as a divide-by-2, divide-by-5 or any combination of both. The 74LS390 is a very flexible dual decade driver IC with a large number of "divide-by" combinations available ranging form divide-by-2, 4, 5, 10, 20, 25, 50, and 100.
Frequency Dividers
This ability of the ripple counter to truncate sequences to produce a "divide-by-n" output means that counters and especially ripple counters, can be used as frequency dividers to reduce a high clock frequency down to a more usable value for use in digital clocks and timing applications. For example, assume we require an accurate 1Hz timing signal to operate a digital clock.
We could quite easily produce a 1Hz square wave signal from a standard 555 timer chip but the manufacturers data sheet tells us that it has a typical 1-2% timing error depending upon the manufacturer, and at low frequencies a 2% error at 1Hz is not good. However the data sheet also tells us that the maximum operating frequency of the 555 timer is about 300kHz and a 2% error at this high frequency would be acceptable. So by choosing a higher timing frequency of say 262.144kHz and an 18-bit ripple (Modulo-18) counter we can make a precision 1Hz timing signal as shown below.
Simple 1Hz timing signal using an 18-bit asynchronous ripple counter/divider.
This is of course a very simple example of how to produce accurate frequencies, but by using high frequency crystal oscillators and multi-bit frequency dividers, precision frequency generators can be produced for for a range of applications ranging from clocks or watches to event timing and even electronic piano/synthesizer music applications.
Unfortunately one of the main disadvantages with asynchronous counters is that there is a small delay between the arrival of the clock pulse at its input and it being present at its output due to the internal circuitry of the gate. In asynchronous circuits this delay is called the Propagation Delay giving the asynchronous ripple counter the nickname of "propagation counter" and in some high frequency cases this delay can produce false output counts.
In large bit ripple counter circuits, if the delay of the separate stages are all added together to give a summed delay at the end of the counter chain the difference in time between the input signal and the counted output signal can be very large. This is why the Asynchronous Counter is generally not used in high frequency counting circuits were large numbers of bits are involved.
Also, the outputs from the counter do not have a fixed time relationship with each other and do not occur at the same instant in time due to their clocking sequence. In other words the output frequencies become available one by one, a sort of domino effect. Then, the more flip-flops that are added to an asynchronous counter chain the lower the maximum operating frequency becomes to ensure accurate counting. To overcome the problem of propagation delay Synchronous Counters were developed.
Then to summarise:
Asynchronous Counters can be made from Toggle or D-type flip-flops.
They are called asynchronous counters because the clock input of the flip-flops are not all driven by the same clock signal.
Each output in the chain depends on a change in state from the previous flip-flops output.
Asynchronous counters are sometimes called ripple counters because the data appears to "ripple" from the output of one flip-flop to the input of the next.
They can be implemented using "divide-by-n" circuits.
Truncated counters can produce any modulus number count.
Disadvantages of Asynchronous Counters:
An extra "re-synchronizing" output flip-flop may be required.
To count a truncated sequence not equal to 2n, extra feedback logic is required.
Counting a large number of bits, propagation delay by successive stages may become undesirably large.
This delay gives them the nickname of "Propagation Counters".
Counting errors at high clocking frequencies.
Synchronous Counters are faster using the same clock signal for all flip-flops.
Binary Synchronous Counter
In the previous Asynchronous binary counter tutorial, we saw that the output of one counter stage is connected directly to the clock input of the next counter stage and so on along the chain, and as a result the asynchronous counter suffers from what is known as "Propagation Delay" in which the timing signal is delayed a fraction through each flip-flop.
However, with the Synchronous Counter, the external clock signal is connected to the clock input of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time giving a fixed time relationship. In other words, changes in the output occur in "synchronization" with the clock signal. This results in all the individual output bits changing state at exactly the same time in response to the common clock signal with no ripple effect and therefore, no propagation delay.
Binary 4-bit Synchronous Counter
It can be seen that the external clock pulses (pulses to be counted) are fed directly to each J-K flip-flop in the counter chain and that both the J and K inputs are all tied together in toggle mode, but only in the first flip-flop, flip-flop A (LSB) are they connected HIGH, logic "1" allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal, advancing one state for each pulse.
The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A, but the J and K inputs of flip-flops C and D are driven from AND gates which are also supplied with signals from the input and output of the previous stage. If we enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are "HIGH" we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time. As there is no propagation delay in synchronous counters because all the counter stages are triggered in parallel the maximum operating frequency of this type of counter is much higher than that of a similar asynchronous counter.
Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( "0000" ) to 15 ( "1111" ). Therefore, this type of counter is also known as a 4-bit Synchronous Up Counter.
As synchronous counters are formed by connecting flip-flops together and any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter, the modulo's or "MOD" number still applies as it does for asynchronous counters so a Decade counter or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences.
Decade 4-bit Synchronous Counter
A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. After reaching the count of "1001", the counter recycles back to "0000". We now have a decade or Modulo-10 counter.
Decade 4-bit Synchronous Counter
The additional AND gates detect when the sequence reaches "1001", (Binary 10) and causes flip-flopFF3 to toggle on the next clock pulse. Flip-flop FF0 toggles on every clock pulse. Thus, the count starts over at "0000" producing a synchronous decade counter. We could quite easily re-arrange the additionalAND gates to produce other counters such as a Mod-12 Up counter which counts 12 states from"0000" to "1011" (0 to 11) and then repeats making them suitable for clocks.
Synchronous Counters use edge-triggered flip-flops that change states on either the "positive-edge" (rising edge) or the "negative-edge" (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. Generally, synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal.
It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but this makes it easier to link counters together because the most significant bit (MSB) of one counter can drive the clock input of the next. This works because the next bit must change state when the previous bit changes from high to low - the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays.
Then to summarise:
Synchronous Counters can be made from Toggle or D-type flip-flops.
They are called synchronous counters because the clock input of the flip-flops are clocked with the same clock signal.
Due to the same clock pulse all outputs change simultaneously.
Synchronous counters are also called parallel counters as the clock is fed in parallel to all flip-flops.
Synchronous binary counters use both sequential and combinational logic elements.
The memory section keeps track of the present state.
The sequence of the count is controlled by combinational logic.
Advantages of Synchronous Counters:
Synchronous counters are easier to design.
With all clock inputs wired together there is no inherent propagation delay.
Overall faster operation may be achieved compared to Asynchronous counters.
Count Down Counter
As well as counting "up" from zero and increase, or increment to some value, it is sometimes necessary to count "down" from a predetermined value to zero and to produce an output that activates when the zero count or other pre-set value is reached. This type of counter is normally referred to as a Down Counter, (CTD). In a binary or BCD down counter, the count decreases by one for each external clock pulse from some preset value. Special dual purpose i.c's such as the TTL 74LS193 or CMOS CD4510 are 4-bit binary Up or Down counters which have an additional input pin to select either the up or down count mode.
4-bit Count Down Counter
In the 4-bit counter above the output of each flip-flop changes state on the falling edge (1-to-0 transition) of the CLK input which is triggered by the Q output of the previous flip-flop, rather than by the Q output as in the up counter configuration. As a result, each flip-flop will change state when the previous one changes from 0 to 1 at its output, instead of changing from 1 to 0.
Bidirectional Counter
Both Synchronous and Asynchronous counters are capable of counting "Up" or counting "Down", but their is another more "Universal" type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters. Bidirectional counters, also known as Up/Down counters, are capable of counting in either direction through any given count sequence and they can be reversed at any point within their count sequence by using an additional control input as shown below.
Synchronous 3-bit Up/Down Counter
The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0) but generally, bidirectional counters can be made to change their count direction at any point in the counting sequence. An additional input determines the direction of the count, either Up or Down and the timing diagram gives an example of the counters operation as this Up/Down input changes state.
Nowadays, both up and down counters are incorporated into single IC that is fully programmable to count in both an "Up" and a "Down" direction from any preset value producing a complete Bidirectional Counter chip. Common chips available are the 74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a fully synchronous Up/Down binary counter and the CMOS 4029 4-bit Synchronous Up/Down counter.
Many a time we forget to switch off the motor pushing water into the overhead tank (OHT) in our households. As a result, water keeps overflowing until we notice the overflow and switch the pump off As the OHT is usually kept on the topmost floor, it is cumbersome to go up frequently to check the water level in the OHT. Here’s a microcontroller-based water level controller-cum-motor protector to solve this problem. It controls ‘on’ and ‘off ’ conditions of the motor depending upon the level of water in the tank. The status is displayed on an LCD module. The circuit also protects the motor from high voltages, low voltages, fluctuations of mains power and dry running.
Circuit description Fig. 1 shows the circuit of the microcontroller-based water level controller-cum-motor protector. It comprises operational amplifier LM324, microcontroller AT89C51, optocoupler PC817, regulator 7805, LCD module and a few discrete components. The AT89C51 (IC2) is an 8-bit microcontroller with four ports (32 I/O lines), two 16-bit timers/ counters, on-chip oscillator and clock circuitry. Eight pins of port-1 and three pins of port-3 are interfaced with data and control lines of the LCD module. Pins P3.0, P3.1 and P3.6 are connected to RS (pin 4), R/W (pin 5) and E (pin 6) of the LCD, respectively. Pin EA (pin 31) is strapped to Vcc for internal program executions. Switch S2 is used for backlight of the LCD module. Power-on-reset is achieved by connecting capacitor C8 and resistor R14 to pin 9 of the microcontroller. Switch S1 is used for manual reset. The microcontroller is operated with a 12MHz crystal. Port pins P2.0 through P2.2 are used to sense the water level, while pins P2.3 and P2.4 are used to sense the under-voltage and over-voltage, respectively. Pin P3.4 is used to control relay RL1 with the help of optocoupler IC3 and transistor T5 in the case of under-voltage, over-voltage and different water level conditions. Relay RL1 operates off a 12V supply. Using switch S3, you can manually switch on the motor. The LM324 (IC1) is a quad operational amplifier (op-amp). Two of its op-amps are used as comparators to detect under- and over-voltage. In normal condition, output pin 7 of IC1 is low, making pin P2.3 of IC2 high. When the voltage at pin 6 of N1 goes below the set reference voltage at pin 5 (say, 170 volts), output pin 7 of N1 goes high. This high output makes pin P2.3 of IC2 low, which is sensed by the microcontroller and the LCD module shows ‘low voltage.’ In normal condition, pin 1 of N2 is high. When the voltage at pin 2 of N2 goes above the set voltage at pin 3, output pin 1 of N2 goes low. This low signal is sensed by the microcontroller and the LCD module shows ‘high voltage.’
Presets VR1 and VR2 are used for calibrating the circuit for under-and over-voltage, respectively. The AC mains is stepped down by transformer X1 to deliver a secondary output of 12V at 500 mA. The transformer output is rectified by a full-wave bridge rectifier comprising diodes D5 through D8, filtered by capacitor C2, and used for the under- and over-voltage detection circuitry. The transformer output is also rectified by a full-wave bridge rectifier comprising diodes D1 through D4, filtered by capacitor C1 and regulated by IC4 to deliver regulated 5V for the circuit.
When water in the tank rises to come in contact with the sensor, the base of transistor BC548 goes high. This high signal drives transistor BC548 into saturation and its collector goes low. The low signal is sensed by port pins of microcontroller IC2 to detect empty tank, dry sump and full tank, respectively.
Operation When water in the tank is below sensor A, the motor will switch on to fill water in the tank. The LCD module will show ‘motor on.’ The controller is programmed for a 10-minute time interval to check the dry-run condition of the motor. If water reaches sensor B within 10 minutes, the microcontroller comes out of the dry-run condition and allows the motor to keep pushing water in the tank. The motor will remain ‘on’ until water reaches sensor C. Then it will stop automatically and the microcontroller will go into the standby mode. The LCD module will show ‘tank full’ followed by ‘standby mode’ after a few seconds. The ‘standby mode’ message is displayed until water in the tank goes below sensor A. In case water does not reach sensor B within 10 minutes, the microcontroller will go into the dry-running mode and stop the motor for 5 minutes, allowing it to cool down. The LCD module will show ‘dry-sump1.’ After five minutes, the microcontroller will again switch on the motor for 10 minutes and check the status at sensor B. If water is still below sensor B, it will go into the dry-running mode and the LCD module will show ‘dry-sump2.’ The same procedure will repeat, and if the dry-run condition still persists, the display will show ‘dry-sump3’ and the microcontroller will not start the motor automatically. Now you have to check the line for water and manually reset the microcontroller to start operation. In the whole procedure, the microcontroller checks for high and low voltages. For example, when the voltage is high, it will scan for about two seconds to check whether it is a fluctuation. If the voltage remains high after two seconds, the microcontroller will halt running of the motor. Now it will wait for the voltage to settle down. After the voltage becomes normal, it will still check for 90 seconds whether the voltage is normal or not. After normal condition, it will go in the standby mode and start the aforementioned procedure.
As the sources of conventional energy deplete day by day, resorting to alternative sources of energy like solar and wind energy has become need of the hour. Solar-powered lighting systems are already available in rural as well as urban areas. These include solar lanterns, solar home lighting systems, solar streetlights, solar garden lights and solar power packs. All of them consist of four components: solar photovoltaic module, rechargeable battery, solar charge controller and load. In the solar-powered lighting system, the solar charge controller plays an important role as the system’s overall success depends mainly on it. It is considered as an indispensable link between the solar panel, battery and load.
The microcontroller-based solar charge controller described here has the following features:
1. Automatic dusk-to-dawn operation of the load 2. Built-in digital voltmeter (0V-20V range) 3. Parallel- or shunt-type regulation 4. Overcharge protection 5. System status display on LCD 6. Deep-discharge protection 7. Low battery lock 8. Charging current changes to ‘pulsed’ at full charge 9. Low current consumption 10. Highly efficient design based on microcontroller 11. Suitable for 10-40W solar panels for 10A load
The circuit of the solar charge controller is shown in Fig. 1. It comprises microcontroller AT89C2051, serial analogue-to-digital converter ADC0831, optocoupler MCT2E, regulator 7805, MOSFETs BS170 and IRF540N, transistor BC547, LCD and a few discrete components. Component description is given below.
Microcontroller. Microcontroller AT89C2051 is the heart of the circuit. It is a low-voltage, high-performance, 8-bit microcontroller that features 2 kB of Flash, 128 bytes of RAM, 15 input/output (I/O) lines, two 16-bit timers/counters, a five-vector two-level interrupt architecture, a full-duplex serial port, a precision analogue comparator, on-chip oscillator and clock circuitry. A 12MHz crystal is used for providing the basic clock frequency. All I/O pins are reset to ‘1’ as soon as RST pin goes high. Holding RST pin high for two machine cycles, while the oscillator is running, resets the device. Power-on reset is derived from resistor R1 and capacitor C4. Switch S2 is used for manual reset. Serial ADC. The microcontroller monitors the battery voltage with the help of an analogue-to-digital converter. The ADC0831 is an 8-bit successive approximation analogue-to-digital converter with a serial I/O and very low conversion time of typically 32 μs. The differential analogue voltage input allows increase of thecommon-mode rejection and offsetting of the analogue zero input voltage. Inaddition, the voltage reference input can be adjusted to allow encoding of anysmaller analogue voltage span to the full eight bits of resolution. It is available in an 8-pin PDIP package and can be interfaced to the microcontroller with only three wires. LCD module. The system status and battery voltage are displayed on an LCD based on HD44780 controller. The backlight feature of the LCD makes it readable even in low light conditions. The LCD is used here in 4-bit mode to save the microcontroller’s port pins. Usually the 8-bit mode of interfacing with a microcontroller requires eleven pins, but in 4-bit mode the LCD can be interfaced to the microcontroller using only seven pins. Solar panel. The solar panel used here is meant to charge a 12V battery and the wattage can range from 10 to 40 watts. The peak unloaded voltage output of the solar panel will be around 19 volts. Higher-wattage panels can be used with some modifications to the controller unit. Rechargeable battery.The solar energy is converted into electrical energy and stored in a 12V lead-acid battery. The ampere-hour capacity ranges from 5 Ah to 100 Ah. Dusk-to-dawn sensor.Normally, in a solar-photovoltaic-based installation—for example, solar home lighting system, solar lantern or solar streetlight—the load (the light) is switched on at dusk (evening) and switched off at dawn (morning). During daytime, the load is disconnected from the battery and the battery is recharged with current from the solar panel. The microcontroller needs to know the presence of the solar panel voltage to decide whether the load is to be connected to or disconnected from the battery, or whether the battery should be in charging mode or discharging mode. A simple sensor circuit is built using a potential divider formed around resistors R8 and R9, zener diode ZD1 and transistor T1 for the presence of panel voltage. Charge control.Relay RL1 connects the solar panel to the battery through diode D1. Under normal conditions, it allows the charging current from the panel to flow into the battery. When the battery is at full charge (14.0V), the charging current becomes ‘pulsed.’ To keep the overall current consumption of the solar controller low, normally-closed (N/C) contacts of the relay are used and the relay is normally in de-energised state. Load control.One terminal of the load is connected to the battery through fuse F1 and another terminal of the load to an n-channel power MOSFET T3. MOFETs are voltage-driven devices that require virtually no drive current. The load current should be limited to 10A. One additional MOSFET is connected in parallel for more than 10A load current.
Circuit description
Basically, there are two methods of controlling the charging current: series regulation and parallel (shunt) regulation. A series regulator is inserted between the solar panel and the battery. The series type of regulation ‘wastes’ a lot of energy while charging the battery as the control circuitry is always active and series regulator requires the input voltage to be 3-4 volts higher than the output voltage. The current and voltage output of a solar panel is governed by the angle of incidence of light, which keeps varying. Parallel regulation is preferred in solar field. In parallel regulation, the control circuitry allows the charging current (even in mA) to flow into the battery and stop charging once the battery is fully charged. At this stage, the charging current is wasted by converting into heat (current is passed through low-value, high-wattage resistor); this part of the regulation dissipates a lot of heat. In this project, we have used parallel regulation technique but instead of wasting the charging current as heat, we have made it pulsed and applied to the battery to keep the battery topped-up. After power-on, the microcontroller reads the battery voltage with the help of the ADC and displays the values on the LCD. It monitors the input signal from the dusk-to-dawn sensor and activates the load or charging relay RL1 accordingly. The digital voltmeter works up to 20V. As Vref of the ADC is connected to VCC (5V), the input voltage to the ADC cannot exceed +5V. A potential divider is used at pin 2 of the ADC (IC2) using resistors R5, R6 and R7 to scale down the voltage from 0V-20V to 0V-05V. The ADC output is multiplied four times and displayed on the LCD as battery voltage. When the solar panel voltage is present, the dusk-to-dawn sensor provides a signal to the microcontroller, which then displays ‘charging’ message on the LCD. During charging, the battery voltage is continuously monitored. When the voltage reaches 14.0V, the microcontroller interrupts the charging current by energising the relay, which is connected to MOSFET BS170 (T2), and starts a 5-minute timer. During this stage, the LCD shows “battery full.” After five minutes, the relay reconnects the panel to the battery. This way, the charging current is pulsed at the intervals of five minutes and the cycle repeats until the panel voltage is present. When the panel voltage falls below the zener diode (ZD1) voltage of the dusk-to-dawn sensor, the microcontroller senses this and activates the load by switching on MOSFET T3 via optocoupler IC3 and “load on” message is displayed. In this mode, the microcontroller monitors for low battery. When the battery voltage drops below 10 volts, the microcontroller turns off the load by switching off MOSFET T3 and “battery low—load off” message is displayed.
Normally, when the load is switched off, the battery voltage tends to rise back and the load oscillates between ‘on’ and ‘off ’ states. To avoid this, the microcontroller employs a hysteresis control by entering into a ‘lock’ mode during low-battery state and comes out of the lock mode when the dusk-to-dawn sensor receives the panel voltage (the next morning). During lock mode, the microcontroller keeps converting the ADC value and displays the battery voltage on the LCD.
